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ps3540-1100 2365 ne hopkins court pullman, wa 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advanced hardware architectures preliminary * product specification AHA3540 40 mbytes/sec aldc data compression coprocessor ic * this specification represents a product still in the design cycle, undergoing testing processes, any specifications are based on design goals only. parameters may be subject to change pending completion of characterization.
advanced hardware architectures, inc. ps3540-1100 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions, notations and definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.4.1 port a and port b interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4.2 data expansion during compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4.3 multiple records. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4.4 byte alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 compression operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 compression pass through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.0 decompression operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 decompression pass through . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 decompression output disabled mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.0 microprocessor interface and register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1.3 port a interface fifo access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 register access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 pausing / resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.0 port a and port b configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.0 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 status 0 (stat0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 status 1 (stat1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 port a configuration 0 (acnf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 port a configuration 1 (acnf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.5 port b configuration 0 (bcnf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.6 port b configuration 1 (bcnf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.7 identification (id0, id1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.8 port a polarity (apol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.9 port b polarity (bpol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.10 port a transfer count (atcl0, atcl1, atch0, atch1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 6.11 record count (rcl0, rcl1, rch0, rch1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.12 port b compare count (bccl0, bccl1, bcch0, bcch1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.13 port b transfer count (btcl0, btcl1, btch0, btch1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6.14 port a fifo data access (afif0, afif1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.15 compressed bytes processed (cbpl0, cbpl1, cbph0, cbph1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.16 port a fifo control (afct) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.17 error status (errs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.18 interrupt status 0 (ints0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.19 interrupt status 1 (ints1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.20 command (cmnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.21 record length (rll0, rll1, rlh0, rlh1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.22 data disabled count (ddcl0, ddcl1, ddch0, ddch1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 6.23 error mask (emsk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.24 interrupt mask 0 (imsk0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.25 interrupt mask 1 (imsk1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
advanced hardware architectures, inc. ii ps3540-1100 7.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.2 port a interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.3 port b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.0 aha related technical publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix a: differences between the AHA3540 and ibm aldc1-20s-lp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 a.1 status and interrupt status register differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 a.2 input/output differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
advanced hardware architectures, inc. ps3540-1100 iii figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2: multiple record compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3: port a interface input padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4: tqfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 6: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7: processor read timing, mmode = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8: processor write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 9: processor read timing, mmode = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 10: processor write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11: port a burst write timing, slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12: port a burst read timing, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13: port b burst read timing, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14: port b burst write timing, master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15: port a write timing, fas368 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16: port a read timing, fas368 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17: port b read timing, fas368 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18: port b write timing, fas368 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19: port a write timing, 43c97 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 20: port a read timing, 43c97 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21: port b read timing, 43c97 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 22: port b write timing, 43c97 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 23: AHA3540 tqfp package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
advanced hardware architectures, inc. iv ps3540-1100 tables table 1: microprocessor interface control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 3: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4: processor read timing, mmode = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 5: processor write timing, mmode = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 6: processor read timing, mmode = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7: processor write timing, mmode = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8: port a burst write timing, slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9: port a burst read timing, slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10: port b burst read timing, master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11: port b burst write timing, master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12: port a write timing, fas368 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13: port a read timing, fas368 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 14: port b read timing, fas368 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15: port b write timing, fas368 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16: port a write timing, 43c97 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 17: port a read timing, 43c97 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18: port b read timing, 43c97 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19: port b write timing, 43c97 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 20: tqfp (thin quad flat pack) 14 14 mm package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ps3540-1100 page 1 of 47 advanced hardware architectures, inc. 1.0 introduction AHA3540 is a single chip lossless compression and decompression integrated circuit implementing the industry standard lossless adaptive data compression algorithm, also known as aldc. the device compresses, decompresses or passes through data unchanged depending on the operating mode selected. this device achieves an average compression ratio of 2:1 on typical computer files. the flexible hardware interface makes this part suitable for many applications. AHA3540 is algorithm compatible to the ibm ? aldc device, aldc1-20s-lp, as well as aha?s first generation aldc device, aha3520. files compressed on one device can be interchanged and decompressed on other devices. content addressable memory (cam) within the compression/decompression engine eliminates the need for external srams. included in this specification is a functional overview, operation modes, register descriptions, dc and ac electrical characteristics, ordering information, and a listing of related technical publications. it is intended for hardware and software engineers designing a compression system using AHA3540. aha designs and develops lossless compression, forward error correction and data storage formatter/controller ics. technical publications are available upon request. 1.1 conventions, notations and definitions ? active low signals have an ?n? appended to the end of the signal name. for example, csn and writen. ? ?signal assertion? means the signal is logically true. ? hex values are represented with a prefix of ?0x?, such as register ?0x00?. binary values do not contain a prefix, for example, mmode = 1. ? a prefix or suffix of ?x? indicates a letter missing in a register name or signal name. for example, xcnf0 refers to the acnf0 or bcnf0 register. ? a range of signal names or register bits is denoted by a set of colons between the numbers. most significant bit is always shown first, followed by least significant bit. for example, mdata[7:0] indicates signal names mdata7 through mdata0. ? mega bytes per second is referred to as mbytes/ sec or mb/sec. ? ibm is a registered trademark of ibm. 1.2 features performance: 40 mb/s data compression, decompression or pass-through rate with a single 80 mhz clock; 20 mb/s data compression, decompression or pass- through rate with a single 40 mhz clock 2:1 average compression ratio a four byte record length register allows record lengths up to 4 gigabytes four byte record count register allows multiple record transfers error checking in decompression mode reportable via an interrupt flexibility: polled or interrupt driven i/o programmable polarity for dma control signals dma fifo access via microprocessor port at port a interface system interface: single chip data compression solution two selectable microprocessor interfaces programmable interrupts interfaces directly with industry standard scsi chips, fas368, aic-43c97c and aic-33c94c others: open standard aldc adaptive lossless compression algorithm complies to qic-154, ecma 222, ansi x3.280-1996 and iso 15200 standard specifications algorithm compatible to ibm aldc1-20s-ha, ibm aldc1-20s-lp and aha3520 100 pin package in 14 14 mm tqfp body lower power 3.3 volt device 1.3 applications tape drives network communications ? wired and wireless
page 2 of 47 ps3540-1100 advanced hardware architectures, inc. 1.4 functional description AHA3540 is a compression/decompression device residing between the host interface, usually scsi, and the buffer manager asic. major blocks in this device are the microprocessor interface, port a interface, port b interface, and the compression/ decompression engine. the microprocessor interface provides status and control information by register access. port a and port b interfaces are configurable for polarity, handshaking modes, and other options. the operating mode establishes the direction of both the port a and port b interfaces. compression or compression pass through sets the port a interface as an input and the port b interface as an output. conversely decompression or decompression pass through sets the port a interface as an output and the port b interface as an input. decompression output disabled mode allows the device to decompress a user programmed number of records while dumping the uncompressed data, then automatically begin outputting the remaining uncompressed records. a four byte record length register and a four byte record count register allow the user to partition the data into multiple records. compression pass through mode and decompression pass through modes allow data transfers through the device without changing the data. both interfaces, port a and port b, have selectable transfer modes. figure 1: functional block diagram port a dma state machine clock generation port b dma state machine processor interface state machine processor interface aldc core aparity[1:0] adata[15:0] clock port a interface port b interface AHA3540 compression chip acout ard bparity[1:0] bdata[15:0] bcout bcin mcin[1:0] waitn addr[4:0] mmode resetn ireqn awr acin mdata[7:0] ibm ? ibm is a registered trademark of ibm. bwr brd
ps3540-1100 page 3 of 47 advanced hardware architectures, inc. 1.4.1 port a and port b interfaces both port a and port b interfaces are independently configurable via the port a configuration register (acnf), the port a polarity register (apol), the port b configuration register (bcnf), and the port b polarity register (bpol). port a may be configured to operate in burst mode (20 mb/sec, slave), 43c97c mode (40 mb/sec, slave) or fas368 mode (40 mb/sec, slave). port b may be configured to operate in burst mode (20 mb/ sec, master), 43c97c mode (40 mb/sec, master) or fas368 mode (40 mb/sec, master). burst mode is an asynchronous dma transfer mode requiring a request followed by one or more acknowledges. data is latched on the trailing edge of the acknowledge pulses. fas368 mode is a dma transfer mode compatible with fas368 devices. in this mode dacka (acout) is asserted low for the entire burst transfer and 16-bit data is strobed into or out of port a using ard or awr respectively. acout, awr and ard must be programmed as active low signals in the apol register. acin (dreq) must be programmed as active high. port a and port b interfaces both contain sixteen-byte fifos. 1.4.2 data expansion during compression data expansion occurs when the size of the data increases during a compression operation. this typically occurs when the data is compressed prior to input into the chip.the expand status bit is set if the port b transfer count is larger than the port a transfer count register. if data expansion caused the port b transfer count to exceed its maximum 4- byte value then the btc overflow error status gets set. worst case expansion allowable by the algorithm is 12.5% or (9/8 times the uncompressed record length). 1.4.3 multiple records the AHA3540 device has two provisions to manage compressing a block of data into multiple records: automatic segmentation into multiple records at the port a interface and the reset history buffer command. during compression operation, the port a interface automatically partitions the uncompressed data into equal length records according to the record count and record length registers. the two sets of registers determine the number of records and length of each record in the data transfer operation. when compressing multiple records the device retains the contents of the history buffer between records. this usually improves compression ratio by allowing data from the current record to match against data from the previous record. during decompression, the previous record must be decompressed prior to the current record unless the history buffer is reset just before compressing the current record. for example, figure 2 shows three records with a history buffer reset before record three. in this case, record three can be decompressed without previously decompressing records one and two. however, decompressing record two requires decompressing record one first. when processing multiple records ( record count is greater than one), the record length must be greater than 0x22. 1.4.4 byte alignment both the port a and port b interfaces support the insertion and removal of padding bytes to align data transfers to any byte boundary within a two-byte or four-byte wide memory system. figure 3 shows the four padding possibilities. in this figure, padding bytes are designated p i , and normal data bytes are designated d i . four bits within the command register are used to specify the desired input and output padding for a given command. pad bytes are not counted by any of the counters. figure 2: multiple record compression history buffer reset port a uncompressed data (optional) record 1 compressed history buffer reset record 1 port b compressed data record 2 record 3 compressed record 2 compressed record 3
page 4 of 47 ps3540-1100 advanced hardware architectures, inc. figure 3: port a interface input padding 2.0 compression operation 2.1 compression pass through compression pass through mode allows data to enter the port a interface, transfer through the aldc core, and exit through the port b interface unchanged. pass through mode uses the port a transfer counter, port b transfer counter and record length and record count registers. the done status bit and interrupt (if not masked) are set when the transfer completes. 2.2 compression during compression operation, uncompressed data flows into the port a interface, is compressed by the compression engine, and the compressed data transferred out of the port b interface. the device contains a content addressable memory (cam). the cam is the history buffer during compression operation. the compressor appends an end marker control code to the end of the compressed data. it also pads the end of a transfer to a byte boundary with zeroes. the compression engine constantly monitors the performance of compression for expansion during compression operation. when the port b transfer count is larger than the port a transfer count the expand bit in the status 0 register is set indicating data expansion during compression operation. port a interface count increments with each byte received and when this count equals the transfer size, all bytes in this transfer have been received into port a. a compression operation is complete when the last byte transfers out of the port b interface and the record length is zero and the record count is one, thus setting the done status bit and generating a done interrupt if it is not masked. port a data transfers adata [15:8] [7:0] d 1 n+8 n+4 n d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 3 d 5 d 7 d 0 d 2 d 4 d 6 part (a): zero bytes of padding port a data transfers adata [15:8] [7:0] d 0 n+8 n+4 n d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 2 d 4 d 6 p 0 d 1 d 3 d 5 part (b): one byte of padding port a data transfers adata [15:8] [7:0] p 1 n+8 n+4 n d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 1 d 3 d 5 p 0 d 0 d 2 d 4 part (c): two bytes of padding port a data transfers adata [15:8] [7:0] p 1 n+8 n+4 n d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 0 d 2 d 4 p 0 p 2 d 1 d 3 part (d): three bytes of padding
ps3540-1100 page 5 of 47 advanced hardware architectures, inc. 3.0 decompression operation 3.1 decompression pass through decompression pass through mode allows data to enter the port b interface, transfer through the aldc core, and exit through the port a interface unchanged. pass through mode uses the port a transfer counter, port b transfer counter, record length and record count registers. the done status bit and interrupt (if not masked) are set when the transfer completes. 3.2 decompression during decompression mode, compressed data flows into the port b interface and is decompressed. the resulting uncompressed data is transferred out of the port a interface. a decompression operation is complete when the last byte transfers out of the port a interface, thus setting the done status bit and generating a done interrupt if it is not masked. decoder control code errors are generated if invalid control codes are detected in the compressed data stream. this error is reported in the error status register. multiple records can be decompressed by programming the record count register. the record count register decrements every time an end of record is decoded. 3.3 decompression output disabled mode decompression output disabled mode allows the user to program the number of records into the data disable count register to decompress while discarding the output. the device then switches to normal decompression mode and continues to decompress the remaining records determined by the remaining number of records in the record count register, and transfers this data out of port a. 4.0 microprocessor inter- face and register access 4.1 microprocessor interface microprocessor interface configuration is determined by the mmode pin. if mmode is tied high, transfers are controlled by a chip select signal (csn) and a read/write signal (rwn), if mmode is tied low, transfers are controlled by separate read (readn) and write (writen) signals. refer to section 10.0 timing specifications for timing diagrams. table 1: microprocessor interface control signals 4.1.1 interrupts ireqn is the hardware interrupt signal. ireqn is a standard ttl output. when active, it indicates an interrupt is set in the device. the microprocessor can determine the cause of the interrupt by reading the interrupt status register. masking individual interrupts with the interrupt mask register disables particular interrupts from causing the interrupt signal pin to assert (ireqn). the interrupt signals are reset to their inactive state when either a hardware or software reset occurs, new compression operation begins, or by writing a zero to the interrupt status bit. in general, the interrupt status and status bits get set even if the interrupt mask bits are set. the exceptions are the one byte at port b, end of record at port b, one byte at port a, and end of record at port a. if these interrupts are masked, this status information can only be provided at the end of transfer, not at end of records because the aldc core does not identify end of records in the data stream. pin name mmode tied low mmode tied high mcin[0] readn csn mcin[1] writen rwn wa i t n wa i t n wa i t n addr[0] addr[0] = 0 selects register bits 7:0 addr[0] = 1 selects register bits 15:8 addr[0] = 0 selects register bits 15:8 addr[0] = 1 selects register bits 7:0
page 6 of 47 ps3540-1100 advanced hardware architectures, inc. 4.1.2 resets there is a hardware reset signal and a software reset. when the resetn signal is asserted all registers are reset, current operations are cancelled, and the history buffer is cleared. the software reset via the command register does not affect the configuration registers (acnf or bcnf), identification register (id), the polarity registers (apol or bpol), or the command register (cmnd). all other registers are reset, current operations cancelled and the history buffer cleared. section 6.0 register description lists the register values after a hardware reset, software reset command, and after a transfer command. a new transfer command does not reset the data path; therefore, a hardware reset or software reset is generally required prior to issuing a new transfer command. 4.1.3 port a interface fifo access it is possible to access the port a interface fifo from the microprocessor interface. this allows the uncompressed data stream to be altered from the microprocessor. this may be useful to properly handle exception conditions. both read and write accesses are available. only the port a interface fifo is accessible from the microprocessor interface. in order to access the fifo from the microprocessor interface, data transfers on the port a interface must be suspended. the dma device attached to the port a interface must deactivate the dreqa line before attempting to access the fifo from the microprocessor interface. unpredictable results occur if dreqa is active during fifo access from the microprocessor interface. two registers are used to control access to the fifo: the port a fifo control (afct) register and the port a fifo data (afif) register. afif is a two-byte register used to hold data to be written to the port a interface fifo during compression operations and to hold data read from the port a interface fifo during decompression operations. two bits within afct are defined: access port a fifo (accf) and request port a fifo (reqf). the access port a fifo bit must be set for the entire duration of a read or write access to the port a fifo. this bit controls whether the port a fifo is accessed from the port a interface or the microprocessor interface. the reqf bit is used as a semaphore to request a read or a write to the port a interface fifo. read or write is determined by the current command being executed. the fifo can be read only during decompression commands and can be written only during compression commands. writing to the port a interface fifo, assuming a compression or compression bypass operation is being executed, requires the following: 1) suspend transfers on port a interface (dreqa input must be deasserted). 2) write a select port a command. 3) set accf. 4) place data to be written to the original data interface fifo in afif. 5) set reqf. 6) read reqf until reqf returns to a zero. 7) repeat steps 3 to 5 as necessary. 8) clear accf and resume dma operations. reading from the port a interface fifo, assuming a decompression bypass, decompression or decompression output disabled operation is being executed, requires the following: 1) suspend transfers on port a interface (dreqa input must be deasserted). 2) write a select port a command. 3) set accf. 4) set reqf. 5) read reqf until reqf returns zero. reqf is reset when two bytes have been read from the port a interface fifo and placed in afif. 6) read data from afif. 7) repeat steps 3 to 5 as necessary. 8) clear accf and resume dma operations. all port a interface status indicators are updated exactly as if the data is read from or written to the port a interface data bus. for instance: the port a interface transfer count (atc) will increment as bytes are transferred through the microprocessor interface. all status bits (stat0 and stat1) and interrupt status bits (ints) will operate when data is transferred through the microprocessor interface. padding bytes are supported at command boundaries. padding bytes may have to be inserted to ensure that the last transfer from the microprocessor ends on an even-byte boundary.
ps3540-1100 page 7 of 47 advanced hardware architectures, inc. 4.2 register access mmode determines whether addr[0] selects even or odd addressed registers. when mmode = 1 and addr[0]=0, odd addressed registers are accessible. mmode=1 causes addr[0] input signal to be inverted. the registers may not be stable if paused is not set. registers should only be written when they are stable. when writing to registers that are defined as 16- bit registers, both bytes must be written before the register is updated. when writing the 16-bit command register, the command is executed when the most significant byte is written. addr[0] selects between the upper and lower bytes of 16-bit registers. registers in the aldc core require longer to access than the external microprocessor interface permits. therefore, if back to back writes to the same address ever occur, they must be separated by a minimum of 8 clocks. 4.3 pausing / resume when a pause command is issued or an unmasked data transfer interrupt occurs, the device pauses at the next break in the dma handshaking. the following unmasked interrupts cause the device to pause: odt (output disable terminated), eorpa (end of record at port a), bpa (one byte at port a), eorpb (end of record at port b), bpb (one byte at port b), bcmp (port b interface compare), and eord (end of record at decoder). a slave port pauses after acout (dacka) deasserts. for a master port, the paused status bit will get set even if bcout (dreqb) is asserted. the master port may have several transfers in its output pipe. therefore, several transfers could occur before the interface pauses and dreqb remains deasserted. once paused and the last transfer is complete, the data busses are put in high impedance. operation is continued by issuing a resume command registers in the aldc core require longer to access than the external microprocessor interface permits. therefore, these registers must be prefetched for external reads. to assure that the values read from these registers are current, it is recommended that a pause command be issued and paused status read prior to reading these registers. when a pause command is received, it takes up to 40 clock cycles to update these registers. the paused status bit is not set until the registers are updated. additional microprocessor accesses during this time will delay the prefetched reads and paused status. registers that must be prefetched include the compressed bytes processed , error status , interrupt status , record count and data disable count registers. 5.0 port a and port b configuration port a and port b are both 16-bit bidirectional data ports with parity checking and generation. the ports are controlled by the configuration registers acnf[15:0] and bcnf[15:0], and polarity registers apol[7:0] and bpol[7:0].
page 8 of 47 ps3540-1100 advanced hardware architectures, inc. 6.0 register description addr[4:0] mnemonic register name r/w n o t e s register reset value p a g e # mmode = 0 mmode = 1 hardware reset reset command new transfer command 0x00 0x01 stat0 status, byte 0 r 1 0x00 0x00 0x80 9 0x01 0x00 stat1 status, byte 1 r 1, 4 0x0c 0x0c 0000uu00 10 0x00 0x01 acnf0 port a configuration, byte 0 r/w 2 0x00 unchanged unchanged 11 0x01 0x00 acnf1 port a configuration, byte 1 r/w 2 0x00 unchanged unchanged 11 0x00 0x01 bcnf0 port b configuration, byte 0 r/w 3 0x00 unchanged unchanged 11 0x01 0x00 bcnf1 port b configuration, byte 1 r/w 3 0x00 unchanged unchanged 12 0x02 0x03 id0 identification 0 r 1 0x40 0x40 0x40 12 0x03 0x02 id1 identification 1 r 1 0x35 0x35 0x35 12 0x02 0x03 apol port a polarity r/w 2 0xff unchanged unchanged 12 0x03 0x02 res reserved 0x02 0x03 bpol port b polarity r/w 3 0xdf unchanged unchanged 13 0x03 0x02 res reserved 0x04 0x05 atch0 port a transfer count, byte 2 r 1 0x00 0x00 0x00 13 0x05 0x04 atch1 port a transfer count, byte 3 r 1 0x00 0x00 0x00 13 0x04 0x05 rch0 record count, byte 2 r/w 2 0x00 0x00 0x00 14 0x05 0x04 rch1 record count, byte 3 r/w 2 0x00 0x00 0x00 14 0x04 0x05 bcch0 port b compare count, byte 2 r/w 3 0x00 0x00 0x00 14 0x05 0x04 bcch1 port b compare count, byte 3 r/w 3 0x00 0x00 0x00 14 0x06 0x07 atcl0 port a transfer count, byte 0 r 1 0x00 0x00 0x00 13 0x07 0x06 atcl1 port a transfer count, byte 1 r 1 0x00 0x00 0x00 13 0x06 0x07 rcl0 record count, byte 0 r/w 2 0x00 0x00 0x00 14 0x07 0x06 rcl1 record count, byte 1 r/w 2 0x00 0x00 0x00 14 0x06 0x07 bccl0 port b compare count, byte 0 r/w 3 0x00 0x00 0x00 14 0x07 0x06 bccl1 port b compare count, byte 1 r/w 3 0x00 0x00 0x00 14 0x08 0x09 btch0 port b transfer count, byte 2 r 1 0x00 0x00 0x00 15 0x09 0x08 btch1 port b transfer count, byte 3 r 1 0x00 0x00 0x00 15 0x08 0x09 afif0 port a fifo data access, byte 0 r/w 2 0x00 0x00 0x00 15 0x09 0x08 afif1 port a fifo data access, byte 1 r/w 2 0x00 0x00 0x00 15 0x08 0x09 cbph0 compressed bytes processed, byte 2 r 3 0x00 0x00 0x00 16 0x09 0x08 cbph1 compressed bytes processed, byte 3 r 3 0x00 0x00 0x00 16 0x0a 0x0b btcl0 port b transfer count, byte 0 r 1 0x00 0x00 0x00 15 0x0b 0x0a btcl1 port b transfer count, byte 1 r 1 0x00 0x00 0x00 15 0x0a 0x0b afct port a fifo control r/w 2 0x00 0x00 0x00 16 0x0b 0x0a res reserved 2 0x0a 0x0b cbpl0 compressed bytes processed, byte 0 r 3 0x00 0x00 0x00 16 0x0b 0x0a cbpl1 compressed bytes processed, byte 1 r 3 0x00 0x00 0x00 16 0x0c 0x0d errs error status r 1 0x00 0x00 0x00 17 0x0d 0x0c res reserved 0x0e 0x0f ints0 interrupt status, byte 0 r/w 1 0x00 0x00 0x00 17 0x0f 0x0e ints1 interrupt status, byte 1 r/w 1 0x00 0x00 0x00 18 0x10 0x11 cmnd0 command 0 r/w 0x00 0x00 0x00 19 0x11 0x10 cmnd1 command 1 r/w 0x00 0xa0 0x00 19 0x12 0x13 res reserved 0x13 0x12 res reserved 0x14 0x15 rlh0 record length, byte 2 r/w 0x00 0x00 unchanged 20 0x15 0x14 rlh1 record length, byte 3 r/w 0x00 0x00 unchanged 20
ps3540-1100 page 9 of 47 advanced hardware architectures, inc. notes: 1) when cmnd is not a selection command. 2) when cmnd is a select port a configuration command. 3) when cmnd is a select port b configuration command. 4) u identifies a bit that is unchanged. 6.1 status 0 (stat0) read only hardware reset value = 0x00 reset command = 0x00 any status bit which is active when the device pauses, due to an interrupt or pause command, will remain active until there is a resume command. see appendix a.1 for differences between AHA3540 and ibm aldc1-20s-lp. busy - busy. this bit is set when a data transfer operation begins. it is cleared when the data transfer operation completes successfully, when an unmasked error occurs, when a reset occurs. paused - paused. this bit is set when a data transfer operation is currently paused. it is cleared when a paused data transfer operation is resumed, when a reset occurs, or on a new transfer. outdis - output disabled. this bit is set when port a interface output is disabled. it is cleared when port a interface output is re-enabled, when a reset occurs, or on a new transfer. bypass - bypass. this bit is set after a start compression bypass or a start decompression bypass command is written to the command register. it is cleared after a start compression, start decompression, start decompression output disable, when a reset occurs, when an unmasked error occurs, or when a transfer is complete. expand - expansion. this bit is set when the port b transfer count register is larger than the port a transfer count register. it may toggle many times during a compression operation. it is cleared when another data transfer operation begins or when a reset occurs. anyint - any interrupt. this bit is set while an unmasked interrupt is active. cleared on a new transfer, and when all unmasked interrupts have been cleared. anyerr - any error. this bit is set when an unmasked error occurs. it is cleared when a data transfer operation begins or when a reset occurs. done - done. this bit is set when the current data transfer operation is complete. it is cleared when a data transfer operation begins or when a reset occurs. 0x16 0x17 rll0 record length, byte 0 r/w 0x00 0x00 unchanged 20 0x17 0x16 rll1 record length, byte 1 r/w 0x00 0x00 unchanged 20 0x18 0x19 ddch0 data disabled count, byte 2 r/w 0x00 0x00 unchanged 20 0x19 0x18 ddch1 data disabled count, byte 3 r/w 0x00 0x00 unchanged 20 0x1a 0x1b ddcl0 data disabled count, byte 0 r/w 0x00 0x00 unchanged 20 0x1b 0x1a ddcl1 data disabled count, byte 1 r/w 0x00 0x00 unchanged 20 0x1c 0x1d emsk error mask r/w 0x00 0x00 unchanged 21 0x1d 0x1c res reserved 0x1e 0x1f imsk0 interrupt mask 0 r/w 0x00 0x00 unchanged 22 0x1f 0x1e imsk1 interrupt mask 1 r/w 0x00 0x00 unchanged 22 mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x00 0x01 busy paused outdis bypass expand anyint anyerr done addr[4:0] mnemonic register name r/w n o t e s register reset value p a g e # mmode = 0 mmode = 1 hardware reset reset command new transfer command
page 10 of 47 ps3540-1100 advanced hardware architectures, inc. 6.2 status 1 (stat1) read only hardware reset value = 0x0c reset command = 0x0c the status bits bpb , eorpb , bpa and eorpa will only get set after the last word is transferred if the following interrupt mask bits are set: bpbm , eorpbm , bpam and eorpam . if these bits are set, the aldc core provides end of transfer information, but no end of record information. see appendix a.1 for differences between AHA3540 and ibm aldc1-20s-lp. eord - end of record at decoder. this bit is set when the aldc decoder detects an end of record control code in the compressed data stream or when an aldc decoder control code error occurs. this bit is cleared after reset, when the decoder begins processing the first codeword of the next record, or when a new data transfer operation begins. it is valid for decompression and decompression output disable modes. bcmp - port b interface compare. this bit is set when port b transfer count is greater than or equal to port b interface compare count. otherwise, it is cleared. this bit is cleared after reset or when a new data transfer operation begins. this bit is valid for all modes of operation. bpb - one byte at port b. during compression bypass and compression operations, this bit is set at the same time the end of record at port b (stat1[4] and ints1[4]) is set if only one byte at the port b interface is part of the current record. during decompression bypass operation, this bit is set during the last data transfer of the record at the port b interface if only one byte belongs to the current record. this bit is cleared after reset, when a new data transfer operation begins, or when the first byte of the next record is transferred. not valid during decompression and decompression output disable modes. eorpb - end of record at port b. during compression bypass and compression operations, this bit is set when the last byte of a compressed record is transferred out of the port b interface. during decompression bypass operations, this bit is set when the last byte of a record is transferred into the port b interface. this bit is cleared after reset, when a new data transfer operation begins, or when the first byte of the next record is transferred. not valid during decompression and decompression output disable modes. empb - empty at port b. this bit is set when there is no data in the port b interface data path. this bit must be set when writing to the record length register during decompression bypass operation and when writing to the record count register during decompression and decompression output disabled operations. set after reset. empa - empty at port a. this bit is set when there is no data in the port a interface data path. this bit must be set when writing to the record length or record count registers during compression and compression bypass operations. set after reset. bpa - one byte at port a. during compression bypass and compression operations, this bit is set during the last data transfer of the record at the port a interface if only one byte belongs to the current record. during decompression bypass, decompression, and decompression output disabled modes, this bit is set the same time the end of record at port a interface bit (stat1[0] and ints1[0]) is set if only one byte at the port a interface is part of the current record. this bit is cleared after reset, when a new data transfer operation begins, or when the first byte of the next record is transferred. eorpa - end of record at port a. during compression bypass and compression operations, this bit is set each time the record length (rl) is decremented to zero. during decompression bypass, decompression, and decompression output disabled operations, this bit is set when the last byte of a record is transferred out the port a interface. this bit is cleared after reset, when a new data transfer operation begins, or when the first byte of the next record is transferred. mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x01 0x00 eord bcmp bpb eorpb empb empa bpa eorpa
ps3540-1100 page 11 of 47 advanced hardware architectures, inc. 6.3 port a configuration 0 (acnf0) reserved hardware reset value = 0x00 reset command = unchanged 6.4 port a configuration 1 (acnf1) read/write hardware reset value = 0x00 reset command = unchanged parity - parity. when set, parity checking is enabled for the adata[15:0] data bus. when cleared, parity checking is disabled for the adata[15:0] bus. odd - odd. setting this bit along with parity enables odd parity checking and generation on the adata[15:0] data bus. when cleared with parity set even parity checking and generation is enabled on the adata[15:0] data bus. slave - slave. must always be written with a one. mode[2:0] -dma mode. these bits configure the interface dma mode of the port a interface with values as defined below. 6.5 port b configuration 0 (bcnf0) reserved hardware reset value = 0x00 reset command = unchanged mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x00 0x01 reserved mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x01 0x00 parity odd slave mode[2:0] reserved mode[2:0] dma type 000 reserved 001 fas368 mode 010 43c97 ata 011 burst 100 reserved 101 reserved 110 reserved 111 reserved mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x00 0x01 reserved
page 12 of 47 ps3540-1100 advanced hardware architectures, inc. 6.6 port b configuration 1 (bcnf1) read/write hardware reset value = 0x00 reset command = unchanged parity - parity. when set, parity checking is enabled for the bdata[15:0] data bus. when cleared, parity checking is disabled for the bdata[15:0] bus. odd - odd. when set, odd parity checking and generation is used on the bdata[15:0] data bus. when cleared, even parity checking and generation is used on the bdata[15:0] data bus. mode[1:0] -dma mode. these bits configure the interface dma mode of the port b interface with values as defined below. 6.7 identification (id0, id1) read only hardware reset value = 0x3540 reset command = 0x3540 id[15:0] - the bits of this register correspond to the identification code of the chip. this register is accessible when cmnd is not a selection command. 6.8 port a polarity (apol) read/write hardware reset value = 0xff reset command = unchanged the bits of this register correspond to port a interface signals. a set bit programs the corresponding signal to be active low. a cleared bit programs the corresponding signal to be active high. this register is only accessible when cmnd is select port a configuration. mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x01 0x00 parity odd reserved mode[2:0] reserved mode[2:0] dma type 000 reserved 001 fas368 mode 010 43c97 ata 011 burst 100 reserved 101 reserved 110 reserved 111 reserved mmode = 01 0x02 0x03 id[7:0] 0x03 0x02 id[15:8] mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x02 0x03 acin reserved acout awr ard reserved reserved
ps3540-1100 page 13 of 47 advanced hardware architectures, inc. 6.9 port b polarity (bpol) read/write hardware reset value = 0xdf reset command = unchanged the bits of this register correspond to port b interface signals. a set bit programs the corresponding signal to be active low. a cleared bit programs the corresponding signal to be active high.this register is only accessible when cmnd is select port b configuration. 6.10 port a transfer count (atcl0, atcl1, atch0, atch1) read only hardware reset value = 0x00000000 reset command = 0x00000000 port a transfer count low port a transfer count high atc[31:0] - port a transfer count. these registers provide status information on the number of bytes transferred for a current data transfer operation. during a compression operation, atc is incremented as each original data byte is received by the port a interface. when atc equals the product of the record count and record length during compression, all bytes in the compression operation have been received by the AHA3540. during a decompression operation, atc is incremented as each decompressed data byte is sent by the port a interface. this register is only accessible when cmnd is not a selection command. in the case where only one byte is required to complete a transfer operation (i.e., an odd number of bytes in the transfer), the atc is incremented by one after the byte transfers. atc should not be used to determine the decompression operation is complete. instead, use the done status bit and/or interrupt. data blocks of record count times record length must be smaller the (2 32 ? 1) to prevent overflow of this 4-byte transfer count register. reset on new transfer commands. pad bytes are not counted. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x02 0x03 bcin reserved bcout bwr brd reserved mmode = 01 0x06 0x07 atcl[7:0] 0x07 0x06 atcl[15:8] mmode = 01 0x04 0x05 atch[7:0] 0x05 0x04 atch[15:8]
page 14 of 47 ps3540-1100 advanced hardware architectures, inc. 6.11 record count (rcl0, rcl1, rch0, rch1) read/write hardware reset value = 0x00000000 reset command = 0x00000000 record count low record count high rc[31:0] - record count indicates the number of records to be compressed or decompressed. record count must be set to 0x00000001 during decompression bypass. if the record count must be written to during a compression operation, then the empty at port a ( empa ) status bit must be set. if the record count must be written to during a decompression operation, then the empty at port b ( empb ) status bit must be set. 6.12 port b compare count (bccl0, bccl1, bcch0, bcch1) read/write hardware reset value = 0x00000000 reset command = 0x00000000 port b compare count low port b compare count high bcc[31:0] port b compare count register is used to pause the device after a specified number of bytes are transferred at the port b interface. port b compare count is a four byte register with the two most significant bytes contained in port b compare count high (bcch), and the two least significant bytes contained in the port b compare count low register (bccl). mmode = 01 0x06 0x07 rcl[7:0] 0x07 0x06 rcl[15:8] mmode = 01 0x04 0x05 rch[7:0] 0x05 0x04 rch[15:8] mmode = 01 0x06 0x07 bccl[7:0] 0x07 0x06 bccl[15:8] mmode = 01 0x04 0x05 bcch[7:0] 0x05 0x04 bcch[15:8]
ps3540-1100 page 15 of 47 advanced hardware architectures, inc. 6.13 port b transfer count (btcl0, btcl1, btch0, btch1) read only hardware reset value = 0x00000000 reset command = 0x00000000 port b transfer count low port b transfer count high btc[31:0] -port b transfer count. these registers provide status information on the number of bytes transferred for a current data transfer operation. during a compression operation, btc is incremented as each compressed data byte is sent by the port b interface. during a decompression operation, btc is incremented as each compressed data byte is received by the port b interface. this register is only accessible when cmnd is not a selection command. in the special case where only one byte is required to complete a transfer operation (i.e., an odd number of bytes in the transfer), the btc is incremented by one after the byte transfers. btc should not be used to determine the decompression operation is complete. instead, use the done status bit and/or interrupt. data blocks of record count times record length must be smaller than (2 32 ? 1) to prevent overflow of this 4-byte transfer count register. reset by a new compression mode transfer command, but not by a new decompression mode transfer. pad bytes are not counted. 6.14 port a fifo data access (afif0, afif1) read/write hardware reset value = 0x0000 reset command = 0x0000 fa[15:0] - port a fifo data register is a temporary holding register for data to be written to or read from the port a interface fifo. during compression bypass and compression operations, the port a fifo indicates it has received the data by resetting reqf in the afct register. during decompression bypass, decompression, and decompression output disabled operations, data may be read from this register after the port a fifo resets reqf in the afct register. this register is only accessible when cmnd is a select port a configuration command. this register is reset by a new transfer. mmode = 01 0x0a 0x0b btcl[7:0] 0x0b 0x0a btcl[15:8] mmode = 01 0x08 0x09 btch[7:0] 0x09 0x08 btch[15:8] mmode = 01 0x08 0x09 fa[7:0] 0x09 0x08 fa[15:8]
page 16 of 47 ps3540-1100 advanced hardware architectures, inc. 6.15 compressed bytes processed (cbpl0, cbpl1, cbph0, cbph1) read/write hardware reset value = 0x00000000 reset command = 0x00000000 compressed bytes processed low compressed bytes processed high cbpl[31:0] -compressed bytes processed counter. counts the total number of bytes processed by the aldc decoder during decompression and decompression output disabled operations. it can be used in conjunction with the port b transfer count to determine the number of compressed bytes, if any, that reside in the port b interface and aldc core. 6.16 port a fifo control (afct) read/write hardware reset value = 0x00 reset command = 0x00 accf - access fifo. when set, access to the port a fifo is redirected from the port a interface to the microprocessor interface. this bit is cleared after reset or a new transfer. reqf - request to fifo. during compression bypass and compression operations, this bit is set to one requesting a write to the port a fifo. during decompression bypass, decompression, and decompression output disabled operations, this bit is set to one requesting a read from the port a interface fifo. this bit is cleared when the port a fifo has completed the request or after a reset. this register is only accessible when cmnd is a select port a configuration command. reset by a new transfer. mmode = 01 0x0a 0x0b cbpl[7:0] 0x0b 0x0a cbpl[15:8] mmode = 01 0x08 0x09 cbph[7:0] 0x09 0x08 cbph[15:8] mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x0a 0x0b reserved accf reqf
ps3540-1100 page 17 of 47 advanced hardware architectures, inc. 6.17 error status (errs) read only hardware reset value = 0x00 reset command = 0x00 the error status register provides error status bits to the microprocessor. these bits are set regardless of the error mask settings. reset by a new compression mode transfer. aperr - port a interface parity error. this bit is set when a parity error is detected during a transfer into adata[15:0] and the port a interface parity bit is set. it is cleared when a new compression mode transfer begins or when a reset occurs. bperr - port b interface parity error. this bit is set when a parity error is detected during a transfer into bdata[15:0] and the port b interface parity bit is set. it is cleared when a new compression mode transfer begins or when a reset occurs. btco - port b transfer count overflow error. this bit is set when a carry out is detected on the port b transfer count register. it is cleared when a new compression mode transfer begins or when a reset occurs. atco - port a transfer count overflow error. this bit is set when a carry out is detected on the port a transfer count register. it is cleared when a new compression mode transfer begins or when a reset occurs. adcc - aldc decoder control code error. this bit is set during decompression when an invalid control code is detected in the compressed data stream. it is cleared when a new compression mode transfer begins or when a reset occurs. 6.18 interrupt status 0 (ints0) read only hardware reset value = 0x00 reset command = 0x00 interrupt status bits are reset by writing a zero. this is referred to as an interrupt reset. writing a one has no effect. see appendix a.1 for differences between AHA3540 and ibm aldc1-20s-lp. done - done interrupt. this bit is set when data transfer has completed on the port b interface during compression and when data transfer has completed on the port a interface during decompression. it is cleared when a new compression mode transfer begins, when a reset occurs, or by an interrupt reset. paused - paused interrupt. this bit is set by a pause command, or an unmasked data transfer interrupt. it is cleared when a new compression mode transfer begins, when a reset occurs, or by an interrupt reset. odt - output disabled terminated. this bit is set when the end of record of the last suppressed record is processed by the aldc decoder. this bit is cleared after reset, after an interrupt reset is written, or when a new compression mode transfer begins. error - error interrupt. this bit is set when an unmasked error occurs. it is cleared when a new compression mode transfer begins or when a reset occurs. the error status register is used to determine the cause of the error. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x0c 0x0d reserved aperr bperr reserved btco atco adcc reserved mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x0e 0x0f done paused odt reserved error
page 18 of 47 ps3540-1100 advanced hardware architectures, inc. 6.19 interrupt status 1 (ints1) read/write hardware reset value = 0x00 reset command = 0x00 the interrupt status bits bpb , eorpb , bpa and eorpa will only get set after the last word is transferred if the following interrupt mask bits are set: bpbm , eorpbm , bpam and eorpam . if these mask bits are set, the aldc core provides end of transfer information, but no end of record information. see appendix a.1 for differences between AHA3540 and ibm aldc1-20s-lp. eord - end of record at decoder, this bit is set when the aldc decoder detects an end of record control code in the compressed data stream or when an aldc decoder control code error occurs. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. bcmp - port b interface compare. this bit is set when port b transfer count is greater than or equal to port b interface compare count. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. bpb - one byte at port b. during compression bypass and compression operations, this bit is set at the same time the end of record at port b (stat1[4] and ints1[4]) is set if only one byte at the port b interface is part of the current record. during decompression bypass operation, this bit is set during the last data transfer of the record at the port b interface if only one byte belongs to the current record. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. eorpb - end of record at port b. during compression bypass and compression operations, this bit is set when the last byte of a compressed record is transferred out of the port b interface. during decompression bypass operations, this bit is set when the last byte of a record is transferred into the port b interface. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. bpa - one byte at port a. during compression bypass and compression operations, this bit is set during the last data transfer of the record at the port a interface if only one byte belongs to the current record. during decompression bypass, decompression, and decompression output disabled modes, this bit is set the same time the end of record at port a interface bit (stat1[0] and ints1[0]) is set if only one byte at the port a interface is part of the current record. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. eorpa - end of record at port a. during compression bypass and compression operations, this bit is set each time the record length (rl) is decremented to zero. during decompression bypass, decompression, and decompression output disabled operations, this bit is set when the last byte of a record is transferred out the port a interface. this bit is cleared after reset, when an interrupt reset is written, or when a new compression mode transfer begins. mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x0f 0x0e eord bcmp bpb eorpb reserved bpa eorpa
ps3540-1100 page 19 of 47 advanced hardware architectures, inc. 6.20 command (cmnd) read/write hardware reset value = 0x0000 reset command = 0xa000 unspecified opcodes are reserved and may not be written. cmnd[15:0] -command.this register provides for operation as described in the following table. mmode = 01 0x10 0x11 cmnd[7:0] 0x11 0x10 cmnd[15:8] cmnd[15:0] action selection commands 0xc100 select port a configuration. the port a configuration and port a polarity registers are enabled for reads and writes. 0xc200 select port b configuration. the port b configuration and port b polarity registers are enabled for reads and writes. transfer commands (described in sections 2.0 and 3.0) 0x5000-0x500f start compression bypass. ? cmnd[3:2] determines the number of pad bytes to expect at the port a interface. ? cmnd[1:0] determines the number of pad bytes to insert at the port b interface. 0x5800-0x580f start compression. ? cmnd[3:2] determines the number of pad bytes to expect at the port a interface. ? cmnd[1:0] determines the number of pad bytes to insert at the port b interface. 0x6000-0x600f start decompression bypass. ? cmnd[3:2] determines the number of pad bytes to expect at the port b interface. ? cmnd[1:0] determines the number of pad bytes to insert at the port a interface. 0x6800-0x680f start decompression. ? cmnd[3:2] determines the number of pad bytes to expect at the port b interface. ? cmnd[1:0] determines the number of pad bytes to insert at the port a interface. 0x6c00-0x6c0f start decompression output disabled. ? cmnd[3:2] determines the number of pad bytes to expect at the port b interface. ? cmnd[1:0] determines the number of pad bytes to insert at the port a interface. control commands 0x4200 pause. when a data transfer operation is in progress, any current operation steps are completed and the port a interface and port b interface data busses are placed into a high impedance state. the paused interrupt and paused status bits are then set. all data currently being processed by the data transfer operation is preserved. 0x4400-0x440f resume. a previously paused data transfer operation resumes processing. the paused interrupt and paused status bits are cleared and the busy status bit is set. ? resume[3:2] determines the number of pad bytes to expect at the port b interface. ? resume[1:0] determines the number of pad bytes to insert at the port a interface. 0xa000 software reset. the port a configuration , port b configuration , identification , port a polarity , and port b polarity registers are not affected by this command. all other registers are reset, current operations are cancelled, and the history buffer is cleared. twelve clocks are required to complete the reset operation. suspend writing to any registers during this time. 0xa400 reset the history buffer. only use between compression operations. miscellaneous commands 0x0000 nop, no operation is performed.
page 20 of 47 ps3540-1100 advanced hardware architectures, inc. 6.21 record length (rll0, rll1, rlh0, rlh1) read/write hardware reset value = 0x00000000 reset command = 0x00000000 record length low record length high rl[31:0] - the record length register indicates the number of bytes contained in each uncompressed data record for compression bypass and compression operations. this register decrements with each byte transferred into port a. when the record length reaches zero, the port interface bits stat1[8] and ints1[8] are set. during decompression bypass operations, the record length register indicates the total number of bytes to transfer. record length is not used for decompression and decompression output disabled operations. when processing multiple records (record count is greater than one), the record length must be greater than 0x22. if record length = 0x00000000 when a new transfer or resume command are written, the counter rolls over to 0x10000000. when record count is greater than 1, then record length must be greater than 0x22. pad bytes are not counted. 6.22 data disabled count (ddcl0, ddcl1, ddch0, ddch1) read/write hardware reset value = 0x00000000 reset command = 0x00000000 data disabled count low data disabled count high ddc[31:0] - data disabled count.the data disabled count register provides the microprocessor control of the number of records skipped during a start decompression output disabled operation. if the data disabled count is set to zero during a start decompression output disabled operation or the ddc is greater than the record count during a start decompression output disabled operation, then the port a interface output is disabled for the entire transfer. mmode = 01 0x16 0x17 rll[7:0] 0x17 0x16 rll[15:8] mmode = 01 0x14 0x15 rlh[7:0] 0x15 0x14 rlh[15:8] mmode = 01 0x1a 0x1b ddcl[7:0] 0x1b 0x1a ddcl[15:8] mmode = 01 0x18 0x19 ddch[7:0] 0x19 0x18 ddch[15:8]
ps3540-1100 page 21 of 47 advanced hardware architectures, inc. 6.23 error mask (emsk) read/write hardware reset value = 0x00 reset command = 0x00 the error mask register provides error reporting configuration to the microprocessor. if an unmasked error status bit is active, anyerr status and error interrupts are set. errors are masked by setting the appropriate mask bit to one. aperrm -port a interface parity error mask. bperrm - port b interface parity error mask. btcom - port b transfer count overflow error mask. atcom - port a transfer count overflow error mask. adccm - aldc decoder control code error mask. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x1c 0x1d reserved aperrm bperrm reserved btcom atcom adccm reserved
page 22 of 47 ps3540-1100 advanced hardware architectures, inc. 6.24 interrupt mask 0 (imsk0) read/write hardware reset value = 0x00 reset command = 0x00 the interrupt mask 0 register masks the individual interrupts allowing the user to control which ones may cause the interrupt signal pin (ireqn) to assert. for example, if donem and pausedm are set with errorm cleared, only an error interrupt will cause the interrupt signal pin to assert. interrupts are masked by setting the appropriate mask bit to one. donem - done interrupt mask. pausedm -paused interrupt mask. odtm - output disabled terminated mask. errorm -error interrupt mask. 6.25 interrupt mask 1 (imsk1) read/write hardware reset value = 0x00 reset command = 0x00 the interrupt mask 1 register masks the individual interrupts allowing the user to control which ones may cause the interrupt signal pin (ireqn) to assert. interrupts are masked by setting the appropriate mask bit to one. eordm - end of record at decoder interrupt mask. bcmpm - port b interface compare interrupt mask. bpbm - one byte at port b interrupt mask. eorpbm -end of record at port b interrupt mask. bpam - one byte at port a interrupt mask. eorpam -end of record at port a interrupt mask. mmode = bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01 0x1e 0x1f donem pausedm odtm reserved errorm mmode = bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 01 0x1f 0x1e eordm bcmpm bpbm eorpbm reserved bpam eorpam
ps3540-1100 page 23 of 47 advanced hardware architectures, inc. 7.0 signal descriptions this section contains descriptions for all the pins. each signal has a type code associated with it. the type codes are described in the following table. 7.1 microprocessor interface type code description i input only pin o output only pin i/o input/output pin microprocessor interface signal type description default after reset mdata[7:0] i/o microprocessor data bus hi-z mcin[0] i microprocessor interface control pin [0]. if mmode is high this pin is csn. if mmode is low this pin is readn. input mcin[1] i microprocessor interface control pin [1]. if mmode is high this pin is rwn. if mmode is low this pin is writen. input wa i t n o microprocessor output signal. waitn is driven during csn and then goes to tristate with a resistive pullup. high addr[4:0] i microprocessor interface address bus, used to select internal registers. input mmode i microprocessor interface mode selector pin. input resetn i hardware reset signal. input ireqn o interrupt request output signal. high clock i clock input input + tie i these pins must be tied high in the system. input ? tie i these pins must be tied low in the system. input
page 24 of 47 ps3540-1100 advanced hardware architectures, inc. 7.2 port a interface note: refer to section 5.0 port a and port b configuration for configuration of port a control signals. 7.3 port b interface note: refer to section 5.0 port a and port b configuration for configuration of port b control signals. port a interface signal type description default after reset acin i port a interface control input signal. this signal functions as dreqa. polarity is programmed by apol[7]. input acout o port a interface control output signal. this signal functions as dacka. polarity is programmed by apol[5]. high awr o port a interface control output signal. polarity is controlled by apol[4]. high ard o port a interface control output signal. polarity is controlled by apol[3]. high aparity[1:0] i/o when enabled, this pin checks parity on input and generates parity for output for the ad bus. aparity[0] is used for ad[7:0], and aparity[1] is used for ad[15:8]. setting acnf[15]=1 enables aparity. when disabled these pins may be tied high, tied low or not connected. hi-z adata[15:0] i/o port a interface data bus. hi-z port b interface signal type description default after reset bcin i port b interface control input signal. this signal functions as dackb. polarity is programmed by bpol[7]. input bcout o port b interface control output signal. this signal functions as dreqb. polarity is programmed by bpol[5]. low bwr i port b interface control input signal. polarity is controlled by bpol[4]. input brd i port b interface control input signal. polarity is controlled by bpol[3]. input bparity[1:0] i/o when enabled, this pin checks parity on input and generates parity for output for the bd bus. bparity[0] is used for bd[7:0], and bparity[1] is used for bd[15:8]. setting bcnf[15]=1 enables bparity. when disabled these pins may be tied high, tied low or not connected. hi-z bdata[15:0] i/o port b interface data bus. hi-z
ps3540-1100 page 25 of 47 advanced hardware architectures, inc. 8.0 pinout pin tqfp signal pin tqfp signal 99 no connect 49 acin 100 vdd 50 vdd 1 gnd 51 gnd 2 bdata[7] 52 adata[7] 3 bdata[6] 53 adata[6] 4bdata[5] 54+tie 5 bdata[4] 55 adata[5] 6 bdata[3] 56 adata[4] 7 bdata[2] 57 adata[3] 8 vdd 58 vdd 9 gnd 59 gnd 10 bdata[1] 60 adata[2] 11 no connect 61 ard 12 no connect 62 no connect 13 bdata[0] 63 adata[1] 14 bdata[15] 64 adata[0] 15 bdata[14] 65 adata[15] 16 bdata[13] 66 adata[14] 17 bdata[12] 67 adata[13] 18 vdd 68 vdd 19 gnd 69 gnd 20 bdata[11] 70 adata[12] 21 bdata[10] 71 adata[11] 22 bdata[9] 72 adata[10] 23 bdata[8] 73 adata[9] 24 bparity[0] 74 adata[8] 25 bparity[1] 75 aparity[0] 26 vdd 76 vdd 27 gnd 77 gnd 28 no connect 78 aparity[1] 29 ireqn 79 mdata[7] 30 no connect 80 +tie 31 waitn 81 vdd 32 brd 82 mdata[6] 33 bwr 83 mdata[5] 34 bcout 84 mdata[4] 35 resetn 85 mdata[3] 36 +tie 86 acout 37 clk 87 awr 38 gnd 88 gnd 39 vdd 89 vdd 40 addr[4] 90 mcin[0] 41 addr[3] 91 mcin[1] 42 no connect 92 mdata[2] 43 bcin 93 mdata[1] 44 ? tie 94 mdata[0] 45 +tie 95 no connect 46 addr[2] 96 +tie 47 addr[1] 97 +tie 48 addr[0] 98 mmode
page 26 of 47 ps3540-1100 advanced hardware architectures, inc. figure 4: tqfp pinout notes: 1) see appendix a.2 for differences in pinout requirements between the AHA3540 and ibm aldc1-20s-lp. 2) ibm is a registered trademark of ibm 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 aparity[0] adata[8] adata[9] adata[10] adata[11] adata[12] gnd vdd adata[13] adata[14] adata[15] adata[0] adata[1] nc ard adata[2] gnd vdd adata[3] adata[4] adata[5] +tie adata[6] adata[7] gnd 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 vdd acin addr[0] addr[1] addr[2] +tie ?tie bcin nc addr[3] addr[4] vdd gnd clk +tie resetn bcout bwr brd waitn 30 29 28 27 26 nc ireqn nc gnd vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 gnd bdata[7] bdata[6] bdata[5] bdata[4] bdata[3] bdata[2] vdd gnd bdata[1] nc nc bdata[0] bdata[15] bdata[14] bdata[13] bdata[12] vdd gnd bdata[11] bdata[10] bdata[9] bdata[8] bparity[0] bparity[1] 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 vdd gnd aparity[1] mdata[7] +tie vdd mdata[6] mdata[5] mdata[4] mdata[3] acout awr gnd vdd mcin[0] mcin[1] mdata[2] mdata[1] mdata[0] nc 96 97 98 99 100 +tie +tie mmode nc vdd nc = no connect AHA3540a-040 ptc
ps3540-1100 page 27 of 47 advanced hardware architectures, inc. 9.0 electrical specifications 9.1 absolute maximum ratings 9.2 recommended operating conditions 9.3 dc specifications notes: 1) test conditions: worst case compression current; 0ma loads. absolute maximum ratings symbol parameter min max units notes vdd power supply voltage 3.6 volts vpin voltage applied to any signal pin 0 5.5 volts recommended operating conditions symbol parameter min max units notes vdd power supply voltage 3.0 3.6 volts ta ambient temperature 0 +70 c tc case temperature +95 c dc specifications symbol parameter conditions min typ max units notes vil input low voltage 0 0.8 volts vih input high voltage 2.0 3.3 5.5 volts vol output low voltage iol = 4.0 mamps 0 0 0.4 volts voh output high voltage ioh = -0.4 mamps 2.4 3.3 vdd volts iil input low current vin = 0 volts 5 amps iih input high current vin = vdd volts 5 amps iozl output tristate low current vout = 0 volts 20 amps iozh output tristate high current vout = vdd volts 20 amps idda active idd current vdd = 3.6 volts tbd mamps 1 idd supply current (static) tbd mamps iol low level output current tbd mamps ioh high level output current tbd mamps cin input capacitance 3 pf cout output capacitance 6 pf
page 28 of 47 ps3540-1100 advanced hardware architectures, inc. 10.0 timing specifications notes: 1) all ac timings are referenced to 1.4 volts. figure 5: clock timing table 2: clock timing notes: 1) all ac timings are referenced to 1.4 volts 2) rise and fall times are between0.1 vdd and 0.9 vdd. figure 6: reset timing table 3: reset timing number parameter min max units notes 1 clk period 12.5 ns 1 2 clk low pulsewidth 5 ns 1 3 clk high pulsewidth 5 ns 1 4 clk rise time 3 ns 2 5 clk fall time 3 ns 2 number parameter min max units notes 1 resetn pulsewidth 5 clocks 2 resetn delay to csn, readn or writen 3clocks 4 5 3 2 1 clock resetn mcin[0] or mcin[1] 2 1 (csn, readn or writen)
ps3540-1100 page 29 of 47 advanced hardware architectures, inc. figure 7: processor read timing, mmode = 1 table 4: processor read timing, mmode = 1 note: 1) when waitn causes csn to deassert, ignore number 3, otherwise ignore number 6. 2) the device latches addr on the falling edge of csn. the user should latch mdata on the rising edge of csn. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth 3 clocks 1 4 delay from csn deasserted until next csn 1 clock+5 ns 5 csn asserted to waitn asserted 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted 2 clocks 3 clocks+18 ns 8 addr setup to csn asserted 2 ns 2 9 addr hold from csn asserted 6 ns 2 10 mdata valid from csn asserted 2 clocks+15 ns 11 mdata tristate from csn deasserted 3 20 ns 12 mdata hold from csn deasserted 3 20 ns 13 csn asserted to mdata driven 1 clock 14 csn deasserted to waitn tristate 10 ns mcin[1] (rwn) mcin[0] (csn) waitn mdata addr valid valid 12 3 4 5 6 8 9 7 10 11 12 tristate tristate 14 13
page 30 of 47 ps3540-1100 advanced hardware architectures, inc. figure 8: processor write timing, mmode = 1 table 5: processor write timing, mmode = 1 notes: 1) when waitn causes csn to deassert, ignore number 3, otherwise ignore number 6. 2) when a read to a register immediately follows a write to that same register or to the command register, csn must deassert for a minimum of 3 clocks after the write. 3) the device latches addr on the falling edge of csn. number parameter min max units notes 1 rwn setup to csn asserted 4 ns 2 rwn hold from csn asserted 4 ns 3 csn pulsewidth 2 clocks 1 4 delay from csn deasserted until next csn 1 clock+5 ns 2 5 csn asserted to waitn asserted 18 ns 6 csn hold from waitn deasserted 0 ns 1 7 waitn deasserted from csn asserted 1 clock 2 clocks+18 ns 8 addr setup to csn asserted 2 ns 3 9 addr hold from csn asserted 6 ns 3 10 mdata valid before csn deasserted 4 ns 11 mdata hold from csn deasserted 4 ns 12 csn deasserted to waitn tristate 10 ns mcin[1] (rwn) mcin[0] (csn) waitn mdata addr valid valid 12 3 4 5 6 8 9 7 10 11 12
ps3540-1100 page 31 of 47 advanced hardware architectures, inc. figure 9: processor read timing, mmode = 0 table 6: processor read timing, mmode = 0 notes: 1) when waitn causes readn to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of readn. the user should latch mdata on the rising edge of readn. 3) writen must be deasserted during register reads. number parameter min max units notes 1 readn pulsewidth 3 clocks 1 2 delay from readn deasserted until next readn 2clocks 3 readn asserted to waitn asserted 18 ns 4 readn hold from waitn deasserted 0 ns 1 5 waitn deasserted from readn asserted 2 clocks 3 clocks+18 ns 6 addr setup to readn asserted 2 ns 2 7 addr hold from readn asserted 6 ns 2 8 mdata valid from readn asserted 2 clocks+15 ns 9 mdata tristate from readn deasserted 20 ns 10 mdata hold from readn deasserted 3 ns 11 mdata asserted from readn asserted 1 clock 12 readn deasserted to waitn tristate 10 ns 7 mcin[0] (readn) waitn addr mdata valid valid 1 3 6 5 8 9 10 2 4 tristate tristate 11 12 (note 3)
page 32 of 47 ps3540-1100 advanced hardware architectures, inc. figure 10: processor write timing, mmode = 0 table 7: processor write timing, mmode = 0 notes: 1) when waitn causes writen to deassert ignore number 1, otherwise ignore number 4. 2) the device latches addr on the falling edge of writen. 3) readn must be deasserted during register writes. number parameter min max units notes 1 writen pulsewidth 2 clocks 1 2 delay from writen deasserted until next writen 3clocks 3 writen asserted to waitn asserted 18 ns 4 writen hold from waitn deasserted 0 ns 1 5 waitn deasserted from writen asserted 1 clock 2 clocks+18 ns 6 addr setup to writen asserted 2 ns 2 7 addr hold from writen asserted 6 ns 2 8 mdata valid before writen deasserted 4 ns 9 mdata hold from writen deasserted 4 ns 10 writen deasserted to waitn tristate 10 ns mcin[1] (writen) waitn addr mdata valid valid 1 3 6 5 9 2 4 8 7 10 (note 3)
ps3540-1100 page 33 of 47 advanced hardware architectures, inc. figure 11: port a burst write timing, slave mode table 8: port a burst write timing, slave mode notes: 1) these timings are valid for inverted signal polarities. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 40 mhz. number parameter min max notes 1 last dacka asserted to dreqa deasserted, end of burst 0 ns 2 clocks ? 10 ns 1, 2 2 dreqa asserted to first dacka asserted, start of burst 1 clock 1, 2 3 dacka pulsewidth 2 clocks ? 8 ns 2 clocks+8 ns 1, 2 4 dacka deasserted to dacka asserted 2 clocks ? 8 ns 1, 2 5 last dacka deasserted to next dreqa asserted, next burst 2 clocks 1, 2 6 adata (output) driven from dacka asserted 1 clock ? 5 ns 1, 2 7 adata (output) hold from dacka deasserted 1 clock ? 10 ns 1 clock+5 ns 1, 2 8 adata (output) valid from dacka asserted 1 clock+10 ns 1, 2 1 acin (dreqa input) acout (dacka output) awr (output) adata (output) 2 3 5 6 7 tristate tristate 4 valid valid valid 8
page 34 of 47 ps3540-1100 advanced hardware architectures, inc. figure 12: port a burst read timing, slave mode table 9: port a burst read timing, slave mode notes: 1) these timings are valid for inverted signal polarities. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 40 mhz. number parameter min max notes 1 last dacka asserted to dreqa deasserted, end of burst 0 ns 1 clock + 15 ns 1, 2 2 dreqa asserted to first dacka asserted, start of burst 1 clock 1, 2 3 dacka pulsewidth 2 clocks ? 8 ns 2 clocks+8 ns 1, 2 4 dacka deasserted to dacka asserted 2 clocks ? 8 ns 1, 2 5 last dacka deasserted to next dreqa asserted, next burst 2 clocks 1, 2 6 adata (input) valid after dacka asserted 2 clocks ? 18 ns 1, 2 7 adata (input) hold from dacka deasserted 0 1, 2 1 acin (dreqa input) acout (dacka output) ard (output) adata (input) 2 3 5 6 valid valid valid 7 tristate tristate 4
ps3540-1100 page 35 of 47 advanced hardware architectures, inc. figure 13: port b burst read timing, master mode table 10: port b burst read timing, master mode notes: 1) these timings are valid for inverted signal polarities. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 40 mhz. number parameter min max notes 1 last dackb asserted to dreqb deasserted, end of burst 1 clock + 15ns 1, 2 2 dreqb asserted to first dackb asserted, start of burst 1 clock 1, 2 3 dackb pulsewidth 2 clocks 1, 2 4 dackb deasserted to dackb asserted 2 clocks 1, 2 5 last dackb deasserted to next dreqb asserted, next burst 2 clocks 1, 2 6 bdata (output) driven from dackb asserted 2 ns 1, 2 7 bdata (output) hold from dackb deasserted 2 ns 23 ns 1, 2 8 dackb cycle time 4 clocks 1, 2 9 bdata (output) valid from dackb asserted 23 ns 1, 2 1 bcout (dreqb output) bcin (dackb input) bdata (read, output) 2 3 valid 5 7 6 tristate tristate 4 8 valid valid 9
page 36 of 47 ps3540-1100 advanced hardware architectures, inc. figure 14: port b burst write timing, master mode table 11: port b burst write timing, master mode notes: 1) these timings are valid for inverted signal polarities. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 40 mhz. number parameter min max notes 1 last dackb asserted to dreqb deasserted, end of burst 1 clock + 15ns 1, 2 2 dreqb asserted to first dackb asserted, start of burst 1 clock 1 3 dackb pulsewidth 2 clocks 1 4 dackb deasserted to dackb asserted 2 clocks 1 5 last dackb deasserted to next dreqb asserted, next burst 2 clocks 1 6 bdata (input) valid before dackb deasserted 4 ns 1 7 bdata (input) hold from dackb deasserted 8 ns 1 8 dackb cycle time 4 clocks 1 1 bcout (dreqb output) bcin (dackb input) bdata (write, input) 2 3 valid valid valid 5 7 6 tristate tristate 4 8
ps3540-1100 page 37 of 47 advanced hardware architectures, inc. figure 15: port a write timing, fas368 slave mode table 12: port a write timing, fas368 slave mode notes: 1) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqa asserted to dacka asserted 2 clocks 2 2 dacka deasserted to dreqa asserted 2 ns 3 awr asserted to dreqa deasserted 12 ns 2 4 dacka deasserted to dacka asserted 4 clocks ? 5 ns 2 5 awr asserted to awr asserted 4 clocks ? 4 ns 2 6 dacka asserted to awr asserted 4 clocks ? 5 ns 2 7 awr asserted pulsewidth 2 clocks ? 2 ns 2 8 awr deasserted pulsewidth 2 clocks ? 2 ns 2 9 awr deasserted to dacka deasserted 2 clocks ? 2 ns 2 10 awr asserted to adata write valid 10 ns 11 awr deasserted to adata write invalid 5 ns 12 dacka deasserted to adata write tristate 15 ns awr adata 3 2 4 12 tristate tristate (output) (write, output) 11 9 10 6 7 8 5 acin (dreqa input) acout (dacka output) 1
page 38 of 47 ps3540-1100 advanced hardware architectures, inc. figure 16: port a read timing, fas368 slave mode table 13: port a read timing, fas368 slave mode notes: 1) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqa asserted to dacka asserted 2 clocks 2 2 dacka deasserted to dreqa asserted 2 ns 3 ard asserted to dreqa deasserted 12 ns 2 4 dacka deasserted to dacka asserted 4 clocks ? 5 ns 2 5 ard asserted to ard asserted 4 clocks ? 4 ns 2 6 dacka asserted to ard asserted 4 clocks ? 5 ns 2 7 ard asserted pulsewidth 2 clocks ? 2 ns 2 8 ard deasserted pulsewidth 2 clocks ? 2 ns 2 9 ardr deasserted to dacka deasserted 2 clocks ? 2 ns 2 10 dacka asserted to adata read driven 2 ns 11 adata read setup to ard deasserted 10 ns 12 adata read hold from ard deasserted 5 ns ard 3 2 4 adata (outputs) (read, input) tristate tristate 9 10 6 7 8 5 11 12 acin (dreqa input) acout (dacka output) 1
ps3540-1100 page 39 of 47 advanced hardware architectures, inc. figure 17: port b read timing, fas368 master mode table 14: port b read timing, fas368 master mode notes: 1) after dreqx becomes inactive, additional brd strobes are ignored and no more transfers occur into or out of the port regardless of dackx operation. 2) timing 9 plus timing 7 must be greater than timing 5. number parameter min max notes 1 dreqb asserted to dackb asserted 0 2 dackb deasserted to dreqb asserted 2 ns 3 brd asserted to dreqb deasserted 12 ns 1 4 dackb deasserted to dackb asserted 40 ns 5 brd asserted to brd asserted 40 ns 6 dackb asserted to bwr asserted 40 ns 7 brd asserted pulsewidth 15 ns 8 brd deasserted pulsewidth 15 ns 9 brd deasserted to dackb deasserted 15 ns 2 10 brd asserted to bdata write valid 10 ns 11 bdata read hold from brd deasserted 5 ns 12 dackb deasserted to bdata read tristate 15 ns brd bdata 3 2 4 12 tristate tristate (input) (read, output) 11 9 10 6 7 8 5 bcout (dreqb output) bcin (dackb input) 1
page 40 of 47 ps3540-1100 advanced hardware architectures, inc. figure 18: port b write timing, fas368 master mode table 15: port b write timing, fas368 master mode notes: 1) after dreqx becomes inactive, additional bwr strobes are ignored and no more transfers occur into or out of the port regardless of dackx operation. 2) timing 9 plus timing 7 must be greater than timing 5. number parameter min max notes 1 dreqb asserted to dackb asserted 0 2 dackb deasserted to dreqb asserted 20 ns 3 bwr asserted to dreqb deasserted 12 ns 1 4 dackb deasserted to dackb asserted 40 ns 5 bwr asserted to bwr asserted 40 ns 6 dackb asserted to bwr asserted 40 ns 7 bwr asserted pulsewidth 15 ns 8 bwr deasserted pulsewidth 15 ns 9 bwr deasserted to dackb deasserted 15 ns 2 10 dackb asserted to bdata write driven 2 ns 11 bdata write setup to bwr deasserted 10 ns 12 bdata write hold from bwr deasserted 2 ns bwr 3 2 4 bdata (input) (write, input) tristate tristate 9 10 6 7 8 5 11 12 bcout (dreqb output) bcin (dackb input) 1
ps3540-1100 page 41 of 47 advanced hardware architectures, inc. figure 19: port a write timing, 43c97 slave mode table 16: port a write timing, 43c97 slave mode notes: 1) in 43c97 ata mode, one more transfer can occur after dreqx is deasserted. in other words, one more transfer controlled by dackx is allowed after dreqx deasserts. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqa asserted to dacka asserted 2 clocks 2 2 dacka deasserted to dreqa asserted 2 clocks ? 5 ns 3 ard or awr asserted to dreqa deasserted 2 clocks + 5 ns 1 4 dacka deasserted to dacka asserted 2 clocks ? 5 ns 2 5 ard or awr asserted to ard or awr asserted 4 clocks ? 4 ns 2 6 dacka asserted to ard or awr asserted 1 clock ? 5 ns 2 7 ard or awr asserted pulsewidth 2 clocks ? 2 ns 2 8 ard or awr deasserted pulsewidth 2 clocks ? 2 ns 2 9 ard or awr deasserted to dacka deasserted 1 clock ? 5 ns 2 10 awr asserted to adata write valid 10 ns 11 awr deasserted to adata write invalid 5 ns 12 dacka deasserted to adata write tristate 10 ns awr adata 3 2 4 12 tristate tristate (output) (write, output) 11 9 10 6 7 8 5 acin (dreqa input) acout (dacka output) 1
page 42 of 47 ps3540-1100 advanced hardware architectures, inc. figure 20: port a read timing, 43c97 slave mode table 17: port a read timing, 43c97 slave mode notes: 1) in 43c97 ata mode, one more transfer can occur after dreqx is deasserted. in other words, one more transfer controlled by dackx is allowed after dreqx deasserts. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqa asserted to dacka asserted 2 clocks 2 2 dacka deasserted to dreqa asserted 2 clocks ? 5 ns 2 3 ard asserted to dreqa deasserted 2 clocks+5ns 1, 2 4 dacka deasserted to dacka asserted 2 clocks ? 5 ns 2 5 ard asserted to ard asserted 4 clocks ? 4 ns 2 6 dacka asserted to ard asserted 1 clock ? 5 ns 2 7 ard asserted pulsewidth 2 clocks ? 2 ns 2 8 ard deasserted pulsewidth 2 clocks ? 2 ns 2 9 ard deasserted to dacka deasserted 1 clock ? 5 ns 2 10 dacka asserted to adata read driven 0 ns 11 adata read setup to ard deasserted 10 ns 12 adata read hold from ard deasserted 5 ns ard 3 2 4 adata (output) (read, input) tristate tristate 9 10 6 7 8 5 11 12 acin (dreqa input) acout (dacka output) 1
ps3540-1100 page 43 of 47 advanced hardware architectures, inc. figure 21: port b read timing, 43c97 master mode table 18: port b read timing, 43c97 master mode notes: 1) after dreqx becomes inactive, additional brd strobes are ignored and no more transfers occur into or out of the port regardless of dackx operation. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqb asserted to dackb asserted 0 2 dackb deasserted to dreqb asserted 2 clocks ? 5 ns 2 3 brd asserted to dreqb deasserted 12 ns 1 4 dackb deasserted to dackb asserted 2 clocks ? 5 ns 2 5 brd asserted to brd asserted 4 clocks 2 6 dackb asserted to brd asserted 5 ns 7 brd asserted pulsewidth 2 clocks ? 5 ns 2 8 brd deasserted pulsewidth 2 clocks ? 5 ns 2 9 brd deasserted to dackb deasserted 5 ns 10 dackb asserted to bdata read driven 0 11 brd asserted to bdata read valid 10 ns 12 bdata read hold from brd deasserted 5 ns 13 dackb deasserted to bdata read tristate 10 ns brd bdata 3 2 4 13 tristate tristate (input) (read, output) 12 9 10 11 6 7 8 5 bcout (dreqb output) bcin (dackb input) 1
page 44 of 47 ps3540-1100 advanced hardware architectures, inc. figure 22: port b write timing, 43c97 master mode table 19: port b write timing, 43c97 master mode notes: 1) after dreqx becomes inactive, additional bwr strobes are ignored and no more transfers occur into or out of the port regardless of dackx operation. 2) the unit clock refers to the clock input. for this interface the maximum clock frequency is 80 mhz. number parameter min max notes 1 dreqb asserted to dackb asserted 0 2 dackb deasserted to dreqb asserted 2 clocks ? 5 ns 2 3 bwr asserted to dreqb deasserted 12 ns 1 4 dackb deasserted to dackb asserted 2 clocks ? 5 ns 2 5 bwr asserted to bwr asserted 4 clocks 2 6 dackb asserted to bwr asserted 5 ns 7 bwr asserted pulsewidth 2 clocks ? 5 ns 2 8 bwr deasserted pulsewidth 2 clocks ? 5 ns 2 9 bwr deasserted to dackb deasserted 5 ns 10 dackb asserted to bdata[15:0] write driven 0 11 bdata[15:0] write setup to bwr deasserted 10 ns 12 bdata[15:0] write hold from bwr deasserted 2 ns 13 dackb asserted to bdata[15:0] write tristate 0 30 ns bwr 3 2 4 bdata 13 (input) (write, input) tristate tristate 9 10 6 7 8 5 11 12 bcout (dreqb output) bcin (dackb input) 1
ps3540-1100 page 45 of 47 advanced hardware architectures, inc. 11.0 packaging figure 23: AHA3540 tqfp package specifications table 20: tqfp (thin quad flat pack) 14 14 mm package dimensions jedec outline mo-136 (all dimensions are in mm) symbol number of pin and specification dimension 100 sb min nom max (lca) 25 (lcb) 25 a1.7 a1 0.05 0.15 a2 1.35 1.4 1.45 d 15.80 16.0 16.20 d1 13.90 14.0 14.10 e 15.80 16.0 16.20 e1 13.90 14.0 14.10 l 0.50 0.60 0.75 p0.50 b 0.17 0.22 0.27 l a a2 a1 (lca) e1 d1 p p d b e (lcb) 76 77 78 79 80 96 97 98 99 100 25 24 23 22 21 AHA3540a-040 ptc
page 46 of 47 ps3540-1100 advanced hardware architectures, inc. 12.0 ordering information 12.1 available parts 12.2 part numbering device number: 3540 revision letter: a package material codes: p plastic package type codes: t t - thin test specifications: c commercial 0 c to +70 c 13.0 aha related technical publications * document in development part number description AHA3540a-040 ptc 40 mbytes/sec aldc data compression coprocessor ic with enhanced features, tqfp aha 3540 a- 040 p t c manufacturer device number revision level speed designation package material package type test specification document # description pb3540 aha product brief ? AHA3540 40 mbytes/sec aldc data compression coprocessor ic abdc17 aha application brief ? differences between AHA3540 and ibm aldc1-20s-lp devices andc18 aha application note ? differences between aha and ibm devices andc24 * aha application note ? AHA3540 designer ? s guide
ps3540-1100 page 47 of 47 advanced hardware architectures, inc. appendix a: differences between the AHA3540 and ibm aldc1-20s-lp a.1 status and interrupt status register differences if the interrupt mask bits bpbm (one byte at port b mask), eorpbm (end of record at port b mask), bpam (one byte at port a mask), eorpam (end of record at port a mask) are set, then the status bits bpb (one byte at port b), eorpb (end of record at port b), bpa (one byte at port a), eorpa (end of record at port a), and the interrupt status bits of the same name are only generated at the end of a transfer and not at end of records. if the interrupts are not masked then these status bits and interrupt status bits will get set at end of records and the device will generated an interrupt and pause. there are two new status bits, empa (empty at port a) and empb (empty at port b). these bits are asserted when there is no data between the pins of the device and the aldc core. a.2 input/output differences there are two new inputs brd (pin 32) and bwr (pin 33) required for the fas368 master mode on port b. in a system that does not use these inputs, they must be tied high or low. they can not be left unconnected. the ibm device requires that these pins be left unconnected. one possible solution for a board that uses both devices is to tie the pins to ground through an appropriate sized resistor.

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